MediaTek collaborates with NTU EECS and Maxeda Technology to introduce a new AI-powered chip design algorithm at the ACM/IEEE Design Automation Conference
This July, MediaTek will be presenting joint research with College of Electrical Engineering & Computer Science, National Taiwan University (NTU EECS) and Maxeda Technology at the ACM/IEEE Design Automation Conference (DAC), the most influential and longest-running conference on Electronic Design Automation (EDA) in the world. As an added distinction, this year’s DAC has selected the said research as one of its inaugural Publicity Papers.
The multiple-objective reinforcement learning algorithm proposed in the research can simultaneously optimize conflicting objectives in chip design in terms of power consumption, efficiency, chip area, yield, etc. It opens the door to significantly reduce development costs, cut down development time, and improve chip performance. The algorithm has already been applied to the creation of the MediaTek Dimensity mobile chip series and will be used in other product lines as well.
“MediaTek strives to stay ahead of the curve in technology,” said SR Tsai, Corporate Senior Vice President of MediaTek’s Central Design Group. “To develop such cutting-edge technology, we employ artificial intelligence in certain aspects of the chip design process to make up for a lack of existing tools. The smart EDA tool we developed with our collaborators has enabled MediaTek Dimensity line-up which outperforms products designed using traditional methods, in terms of power, performance, area, and schedule. We hope this breakthrough will propel AI research towards mainstream applications.”
Along with its collaborators, MediaTek and its advanced technology research subsidiary, MediaTek Research, have achieved breakthroughs and uncovered opportunities for innovation in AI applications by engaging in both basic and applied research to great international acclaim. Their research, titled “Flexible Chip Placement via Reinforcement Learning,” marks the beginning of a new chapter in the incorporation of artificial intelligence into EDA technology.
Now in its 59th year, the Design Automation Conference (DAC), sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), is the top international conference in the field of electronic design automation and the most important annual event for chip circuit design. All manuscripts accepted for publication have undergone a rigorous review process and have a wide and far-reaching international impact. The average acceptance rate is only around 20%, and the acceptance rate for the inaugural publicity paper category is a mere 5%.
Designing and creating circuits is an intricate task that can be challenging for designers without the use of EDA tools. These programs work by converting complex problems in circuit systems into mathematical or logic models, which can then be solved using algorithms. AI entered the picture as the complexity and scale of circuit design reaches an all-time high, and the world’s leading companies have already invested many resources into research and development in AI-assisted EDA.
