MediaTek has a long history of accepted papers and presenting sessions at the International Solid-State Circuits Conference (ISSCC), the foremost global forum for presenting advances in solid-state circuits and systems-on-a-chip, hosted by the IEEE and SSCS. This year, the company was represented by many team members from several of its global offices, with topics covering a wide range of cutting-edge semiconductor technologies, reflecting the breadth of world-class IP MediaTek's talented engineers are involved in creating.Abstracts of two forums presented by MediaTek ASIC team members are detailed below:
Robust Circuit/Architecture Co-Design for Chiplet Integration, presented by WenChou Wu
Abstract:
Homogeneous and heterogeneous chiplet integration is widely recognized as a key design solution driving semiconductor industry forward. However, beyond the advancement of packaging technology, the Multi-Physics integrity such as the Signal Integrity (SI), Power Integrity (PI), Electromagnetic Integrity (EMI), and Thermal Integrity (TI) encountered during chiplet integration are becoming increasingly critical. The success of chiplet integration hinges on these key multi-physics integrity design techniques. In high-performance computing and Cloud AI chips, multiple logic chiplets need to be interconnected through die-to-die links. Adopting 2.5/3D packaging technology to integrate HBM may be mandatory to meet low power and low latency requirements. This necessitates handling high-speed SI issues, logic chip PI and TI issues, and interference problems between digital signals and high-speed analog signals. The aforementioned issues and solutions have been thoroughly discussed in this presentation. Additionally, due to the increasing complexity of multi-physics integrity analysis, we have been exploring the opportunities and challenges of incorporating machine learning techniques for chiplet integration. Some ongoing advancement that serves as a co-pilot for designers have been demonstrated.
Highlights and Challenges in Deploying 100G+ SERDES, presented by Francis Lin
Abstract:
The ever increasing data rate requirements in modern data center and satellite facilities has led to the inevitable adoption of 100G+ per lane Serdes, which presents unique challenges of both on die and off die BW preservation and impairment mitigations. In this discussion we will talk about the difficulties imparted by available technologies today and design approaches to mitigate the risks through system approaches. We'll also talk about what could potentially be achieved with coming technology advancements.
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A shortlist of other staff involvement at the conference includes:
- Hugh Mair co-organized a forum: Efficient chiplets and die-to-die communications
- BorSung Liang presented: Next-Generation Mobile Processors with Large-Language Models (LLMs) and Large Multimodal Models (LMMs), and, Energy Efficient AI Computing Systems for LLMs.
- Yu-Li co-chaired a session on: Frequency Synthesis Session
- Tamer Ali chaired a session on: High-Performance Optical Transceivers, and co-organized a session on Toward Next Generation of Highly Integrated Electrical Optical Transceivers
- ShonHang Wen co-organized: Generative AI for Chip Design Evening Event & chair for Audio Amplifiers Session
Several more MediaTek team members were also involved with these sessions:
- A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC
- A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU
- A 600Gb/s DP-QAM64 Coherent Optical Transceiver Front-End with 4x105GS/s 8b ADC/DAC in 16nm CMOS
- NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices
Follow ISSCC Videos on YouTube to catch replays of this year's sessions.
