By Jerry Chang, Head of Marketing, Americas & Europe, MediaTek
MediaTek's expansion into data center infrastructure represents one of the company's fastest-growing businesses and a key pillar of its strategy to extend AI innovation from the edge to the cloud. At Computex 2026, MediaTek’s Vince Hu went into detail about MediaTek’s growth in this market and how we’re well positioned with the increasing demand for custom data center silicon.
As AI infrastructure spending accelerates, Vince noted that MediaTek raised its AI Data Center ASIC revenue guidance to $2B in 2026. The company sees a $70 to $80 billion AI Data Center solutions total addressable market by 2027 and is targeting 10-15% of that opportunity in the coming years.
The reason customers are coming to MediaTek is not just one capability, but the full stack: custom ASIC design, advanced process technology, packaging, memory, interconnect, and rack-level integration. Vince explained that MediaTek began this journey over a decade ago and has built the technology portfolio and ecosystem relationships needed to help hyperscale customers optimize performance per watt, performance per TCO, and time to market.
We debuted the above animation during Computex — and the reaction said everything. In a room full of journalists and analysts who cover this industry daily, people stopped and watched. Because what you're seeing isn't a concept video. It's a walkthrough of what we actually build. Every stage — from the first custom silicon to the fully integrated rack — is engineering MediaTek delivers today, in production, for the world's most demanding hyperscalers. We've been building this business for over a decade. Here's how it works.
Step 1: Custom ASIC Design
Building a custom XPU begins before any silicon is drawn. MediaTek co-architects customers' custom proprietary technology/IP into a fully realized ASIC, or designs custom accelerators from scratch around their specific workloads. Not only that, we maximize process entitlement to further improve Perf/Watt.
The first is Design-Technology Co-Optimization (DTCO) — working directly with leading fabs to tweak the process itself and extract every last bit of performance the silicon can deliver. We have extensive experience in early node adoption as well, with 10+ tape-outs on TSMC N3, 2+ on N2, and our first A14 test chip taping out later this year. And there is also low-voltage operation. Power scales cubically with voltage, so operating lower has an outsized effect on efficiency. MediaTek's mobile heritage — where low-voltage design is foundational — gives us a head start no data center-only competitor can replicate.
Step 2: Advanced Packaging
Watch the die singulation complete and assembly begin. This is where AI systems are won or lost. The package is the system canvas: where we escape the limits of a single die and bring heterogeneous components together as one coherent engine.
In 2.5D, compute dies and HBM stacks sit side by side on a silicon interposer — achieving enormous bandwidth within a package under 10,000 mm². In 3.5D, vertical die stacking minimizes distances between logic, memory, and I/O to nanometer precision, enabling systems from 10,000 to 20,000 mm² where CPUs, XPUs, HBM, and I/O chiplets are integrated as a single unit.
Step 3: The XPU
The XPU isn't a single die — it's a system built from four elements MediaTek designs together. The compute die delivers the parallel processing density needed for AI training and inference at scale. The memory interface die connects to HBM with flexibility tuned to each model and deployment phase. Ultra high-speed I/O extends the system outward — co-packaged copper (CPC) for short-reach channels, co-packaged optics (CPO) for long-reach. And System-Technology Co-Optimization (STCO) ties the entire package together, unlocking step-function gains that component-by-component design can't achieve.
Step 4: Interconnect
Now watch the data move. MediaTek brings proprietary innovation at every tier. On package, die-to-die interconnect (industry-standard UCIe, or custom M-Link) delivers extreme bandwidth at the lowest energy per bit. On board, chip-to-chip uses High-Speed SerDes and uLED. Off board, rack-level connectivity scales through Ethernet SerDes, NVLink Fusion, and co-packaged optics. And for the longest reaches, optical interconnects extend up to 500 meters — enabling the AI factory architectures that next-generation infrastructure demands.
Step 5: The Rack
The rack is the new unit of compute. What you see in the final frames of the animation isn't the end of the story — it's the product. Every layer engineered above exists to make this moment possible: a fully integrated AI compute system optimized for performance per watt and performance per TCO, under real power and thermal constraints, at hyperscale.
MediaTek is one of the few companies in the world that delivers the entire stack — from custom ASIC through packaging, interconnect, and full rack-level integration. We don't stop at the chip boundary. We architect the rack.
Beyond the XPU. Innovating the fabric of AI scaling.
MediaTek Data Center Solutions: Custom ASIC Design · Packaging · XPU · Interconnect
