At ISSCC 2025, MediaTek's wireline connectivity team presented its best-in-class SerDes performance for 212Gb/s, and 106Gb/s using DSP-based PAM-4 transceiver, with channel reach exceeding 50dB for both speeds. The highest shoreline bandwidth density and competitive power was also demonstrated. With the escalating need for data-intensive applications such as artificial intelligence XPUs, and high-performance computing (HPC) ASICs, off-chip data transfer has become a critical bottleneck. Consequently, wireline serial link data rates of beyond 200 Gb/s is needed to meet the pace of demand.
The large and complex packaging used in these links presents significant signal integrity challenges, primarily substantial channel loss and reflections. To mitigate these issues, sophisticated digital equalization techniques are required. For instance, extended feed-forward equalization (FFE) lengths, floating taps for reflection cancellation, and maximum likelihood sequence detection (MLSD) within RX DSP are essential for addressing severe signal integrity impairments. Furthermore, the analog frontend must provide additional bandwidth and reduced noise impairments as the baud rate of transmitted and received signals doubles. Aggressive design innovations in both the analog frontend and DSP are imperative to achieve competitive performance, area efficiency, and power efficiency in a 200 Gb/s link.
In addition, a second paper was presented detailing a 112 Gb/s DSP-based PAM-4 receiver with an LC-resonator-based CTLE for >52 dB loss compensation in 4 nm FinFET. This technology is essential for keeping pace with the rapid growth of AI accelerators and GPUs, where long-reach, high-speed interconnects with data rates of 100 Gb/s or higher are widely required for applications such as Ethernet/Optical standards or PCIe 7.0.
Despite the latest advances in DSP-based wireline transceivers, the increasing complexity of networking systems demands a breakthrough in SerDes architecture for successful signal transmission over long channels. This work presents an energy-efficient DSP-based 112 Gb/s PAM-4 receiver with a novel CTLE architecture and an analog data path latency reduction technique. The proposed innovations are also directly applicable to upcoming PCIe 7.0 systems for 128 GT/s.
These technical achievements, presented at the world’s foremost annual semiconductor conference, clearly demonstrate how MediaTek provides industry-leading 224G SerDes. This ultra-high-speed wireline technology offers exceptional performance, reliability, and power efficiency per bit, making it ideal for the demands of AI data centers, hyperscale computing, and networking infrastructure.
SerDes expertise is integral to our ASIC offerings, driving the next generation of AI acceleration and various interconnect applications. The 224G SerDes solutions are silicon-proven, and development of the next-generation SerDes is already underway. MediaTek collaborates with major foundries on the most advanced process nodes, chip-to-chip interconnects, high-speed I/O, on-package memory, and ultra-large package designs. This effort also enables MediaTek to optimize performance, power, and area (PPA) through Design Technology Co-Optimization (DTCO) to best meet customers’ domain-specific requirements.
